1. Field of the Invention
The present invention relates to a technique of driving a display panel made of a set of discharge cells each having a memory function and serving as a display element. In particular, the present invention relates to a method of, and an apparatus for, driving an alternating current (AC) type plasma display panel (PDP).
The AC-type PDP applies voltage pulses alternately to a pair of sustaining electrodes to continuously cause discharge in each discharge cell and make the cell emit light. Each discharge lasts one to several microseconds after the application of the voltage pulse. The discharge produces positive charges, i.e., ions, which accumulate on an insulating layer above the sustaining electrode that is receiving a negative voltage. The discharge also produces negative charges, i.e., electrons, which accumulate on the insulating layer above the sustaining electrode that is receiving a positive voltage. These accumulated positive and negative charges are called "wall charges."
When any discharge cell receives a high-voltage pulse (write pulse), the cell discharges and accumulates wall charges. Then, by only applying low-voltage pulses (sustaining pulses) to the cell, the wall charges increase to exceed the discharge threshold of the cell, and the cell starts to discharge. Namely, once write discharge takes place in a given cell to accumulate wall charges therein, the cell continues to discharge only by alternately applying sustain discharge pulses of opposite polarities thereto. This is the memory function or a memory effect. Generally, the AC-type PDPs use the memory effect to display data. Early versions of the AC-type PDPs mostly employed two electrodes to carry out write discharge (addressing discharge) and sustain discharge.
Color PDPs discharge to produce ultraviolet rays, which excite phosphor contained in each discharge cell. The phosphor is vulnerable to positive charges, i.e., ions produced by discharge. The two-electrode PDPs are structured such that hit the ions directly impact the phosphor, shortening the life of the phosphor.
To solve this problem, a 3-electrode surface-discharge structure has been developed. This structure has separate addressing discharge electrodes and sustain discharge electrodes. Phosphor is formed on a counter substrate that is not used for sustain discharge. Among the 3-electrode PDPs, some form first and second sustain discharge electrodes on a substrate and third electrodes on a counter substrate. Others form first to third electrodes on one substrate with the third electrodes being above or below the first and second sustain discharge electrodes.
The present invention is particularly effective when applied to 3-electrode surface-discharge AC-type PDPs.
2. Description of the Related Art
A For an easy understanding of the problems of prior art systems for driving a plasma display panel, the structure and operation of the prior art will be explained with reference to FIGS. 1 through 9.
FIG. 1 is a block diagram schematically showing peripheral circuits for driving a 3-electrode surface-discharge AC-type PDP according to the prior art. Each of addressing electrodes Aj (j=1 to M) is connected to an addressing driver 5 and is individually driven thereby. Each of scanning electrodes Yi (i=1 to N) is connected to a Y scanning driver 3 and is individually driven thereby. The Y scanning driver 3 is connected to a Y common driver 4. To write data in response to an input signal, addressing discharge is needed. Accordingly, the Y scanning driver 3 applies a scan pulse (-Vy) successively to the scanning electrodes Yi. To display the written data, sustain discharge is needed. Accordingly, the Y common driver 4 applies a sustain discharge pulse (Vs) commonly to the scanning electrodes Yi through the Y scanning driver 3. One end of each sustaining electrode Xi (i=1 to N) is connected to a common node, and the common node is connected to an X common driver 2. The X common driver 2 applies a total write discharge pulse (Vs+Vw) or a sustain discharge pulse (Vs) to the sustaining electrodes Xi.
A control circuit 6 controls these drivers and basically consists of a display data controller 7 and a panel controller 8. The display data controller 7 has a frame memory 71 for temporarily storing a frame of display data externally supplied. The display data controller 7 controls the addressing driver 5. The panel controller 8 has a scanning driver controller 81 and a common driver controller 82. The controllers 81 and 82 operate in response to a vertical synchronous signal VSYNC and a horizontal synchronous signal HSYNC that are externally supplied. The scanning driver controller 81 controls the Y scanning driver 3. The common driver controller 82 controls the Y common driver 4 and X common driver 2.
FIG. 2 is a plan view schematically showing the PDP of FIG. 1. Each pair of the scanning electrodes Yi and sustaining electrodes Xi forms a display line. The addressing electrodes Aj are orthogonal to the scanning and sustaining electrodes Yi and Xi, to form discharge cells 101 at the intersections of the electrodes. The discharge cells in the PDP are spatially separated from one another with barriers or ribs 19. The barriers 19 may completely surround and seal each discharge cell 101. In FIG. 2, the barriers 19 are formed only in one direction, and there run gaps in the other direction, to separate the discharge cells 101 from one another.
FIG. 3 is a sectional view taken along one of the addressing electrodes Aj of the PDP of FIG. 2. FIG. 4 is a sectional view taken across the addressing electrodes Aj.
Two glass substrates 11 and 14 that face each other define discharge spaces 10. The front substrate 14 supports the scanning and sustaining electrodes that run in parallel with each other. Each of the scanning and sustaining electrodes consists of a transparent electrode 15 and a bus electrode 16. The transparent electrode 15 is made of, for example, ITO (indium tin oxide) that transmits reflected light from phosphor 13. The bus electrode 16 is laminated on the transparent electrode 15, to prevent a voltage drop due to the transparent electrode 15 that has a relatively large resistance compared with metal wiring. The bus electrode 16 is opaque, and therefore, must be thin so that it will not reduce the display area. The electrodes are covered with a dielectric layer 17, which is covered with an MgO (magnesium oxide) film 18 serving as a protective film.
The front glass substrate 14 faces the back glass substrate 11, which supports the addressing electrodes Aj that are orthogonal to the scanning and sustaining electrodes Yi and Xi. Similar to the scanning and sustaining electrodes, the addressing electrodes are covered with a dielectric layer 12. The barriers 19 are formed between the addressing electrodes Aj, to define the discharge spaces. Between the barriers 19, the phosphor 13 having red, green, and blue light emission properties covers a corresponding one of the addressing electrodes Aj. The two substrates 11 and 14 are assembled so that the ridges of the barriers 19 are tightly in contact with the MgO film 18.
If the PDP is of a transmission type, the back glass substrate 11 is designed to display visible light emitted from the phosphor 13. If the PDP is of a reflection type, the front glass substrate 14 is designed to display reflected light from the phosphor 13. The PDP of FIGS. 3 and 4 is of the reflection type.
FIG. 5 shows waveforms used to drive the PDP of the prior art. This prior art relates to a disclosure in Japanese Unexamined Patent Publication (Kokai) No. 7-160218 corresponding to U.S. Pat. No. 5,446,344. The disclosure is based on an "addressing period/sustain discharge period separation" technique. The technique separates an addressing period for writing display data from a sustain discharge period for displaying the written data. The disclosure employs a "write addressing" technique that uses the addressing period to write display data into selected discharge cells that must emit light accordingly. In FIG. 5, the (a) portion shows a waveform for driving the addressing electrodes Aj, the (b) portion shows a waveform for driving the sustaining electrodes Xi, and the (c) to (e) portions show waveforms for driving the scanning electrodes Y1, Y2, and YN, respectively. Since the sustaining electrodes Xi are commonly connected to one another at one ends thereof, they receive the same waveform.
The waveforms of the (a) to (e) portions of FIG. 5 are for a subfield period to be explained later. Each subfield consists of a reset period, an addressing period, and a sustain discharge period.
In the reset period, a ground voltage is applied to the scanning electrodes Yi. A total write discharge pulse of Vs+Vw (about 300 V) is applied to the sustaining electrodes Xi, and a pulse of Vaw (about 100 V) is applied to the addressing electrodes Aj. As a result, total write discharge takes place in every discharge cell in every display line. The sustaining and addressing electrodes are then set to 0 V to let every discharge cell start self-erase discharge due to potential differences among wall charges accumulated with the total write discharge. After neutralizing space charges and zeroing potential differences among the electrodes, the self-erase discharge ends. The self-erase discharge eliminates the wall charges, thereby resetting and equalizing the distribution of charges among the discharge cells. Namely, the self-erase discharge initializes the discharge cells. The reset period stabilizes write discharge to be carried out in the following addressing period.
In the addressing period, a voltage of -Vsc (-50 V) is first applied to the scanning electrodes Yi, and then, a scanning pulse of -Vy (about -150V) is applied sequentially to the scanning electrodes Yi. At this time, an addressing pulse of Va (about 50 V) is applied to selected ones of the addressing electrodes Aj according to display data, and a voltage of Vx (about 50 V) is applied to the sustaining electrodes Xi. A first stage of addressing discharge takes place between the addressing electrodes Aj and the scanning electrode Yi, and just after that, a second stage of the addressing discharge takes place between the sustaining electrodes Xi and the scanning electrodes Yi, to accumulate wall charges to enable sustain discharge in the following sustain discharge period. The reason why the addressing discharge is carried out in the first and second stages is because a discharge start voltage between the addressing electrodes Aj and the scanning electrodes Yi is different from that between the sustaining electrodes Xi and the scanning electrodes Yi. The same operation is carried out through all of the display lines, to write display data into selected discharge cells, i.e., to accumulate wall charges in the selected discharge cells. This technique of carrying out write discharge in selected discharge cells that are going to display data is the "write addressing" technique. There is an "erase addressing" technique that carries out a total write operation on every discharge cell and then an erase discharge operation in unnecessary cells that do not display data.
In the sustain discharge period, a sustain discharge pulse of Vs (about 180 V) is applied alternately to the scanning electrodes Yi and sustaining electrodes Xi. The discharge cells that have accumulated wall charges due to the selective write operation in the preceding addressing period exceed a discharge start voltage because the sustain discharge pulse Vs adds potential to the wall charges, thereby causing sustain discharge in the cells. On the other hand, the discharge cells that have accumulated no wall charges because no selective write operation has been carried out therein in the preceding addressing period do not exceed the discharge start voltage with the sustain pulse of Vs, thereby causing no sustain discharge therein. Consequently, the sustain discharge makes the discharge cells where the selective write operation has been carried out in the preceding addressing period emit light.
The reset, addressing, and sustain discharge periods form a cycle. To display full-color data on the PDP, it is necessary to display gradations. To display gradations, the cycle serves as a subfield or subframe, and each frame of a screen is divided into subfields that provide different intensity levels. This is an ADS subfield technique disclosed in Japanese Unexamined Patent Publication (Kokai) No. 4-195188. The technique determines the intensity level of a given subfield according to the length of the sustain discharge period of the subfield, i.e., the number of sustain discharge pulses applied to the subfield.
FIG. 6 explains the ADS subfield technique for displaying 256 intensity levels. Each frame is divided into eight subfields SF1, SF2, SF3, SF4, SF5, SF6, SF7, and SF8. These subfields involve an identical reset period and an identical addressing period. They, however, involve different sustain discharge periods having a ratio of 1:2:4:8:16:32:64:128. In each frame, the subfields to be turned on are properly selected to display one of the 256 intensity levels ranging from 0 to 255. The ratio of the sustain discharge periods of the eight subfields of FIG. 6 is merely an example and is optionally set. There is a technique of including some subfields having an identical intensity level in a frame. In each frame, the subfields may be arranged in ascending order, in descending order, or in any other order.
An example of the time allocation of a frame will be explained. In Japan, a television image is rewritten at a frequency of 60 Hz. Accordingly, each frame lasts 16.6 ms (1/60 Hz). If each frame involves 510 sustain discharge pulses, 2 of them are in the subfield SF1, 4 in the subfield SF2, 8 in the subfield SF3, 16 in the subfield SF4, 32 in the subfield SF5, 64 in the subfield SF6, 128 in the subfield SF7, and 256 in the subfield SF8. If each sustain discharge pulse lasts 8 .mu.s, each frame needs 4.08 ms for the 510 sustain discharge pulses. Then, the remaining about 12 ms are for the reset and addressing periods of the subfields. This means that the reset and addressing periods of each subfield must be about 1.5 ms (12 ms/8=1.5 ms). If the reset period needs about 50 .mu.s and if the PDP involves 500 display lines, a write time for each display line in each addressing period is about 3 .mu.s ((1.5 ms-50 .mu.s)/500=2.9 .mu.s).
As shown in FIG. 5, the prior art applies the total write discharge pulse of Vs+Vw (about 300 V) to the sustaining electrodes Xi in the reset period. It was found that applying the total write discharge pulse to the sustaining electrodes destabilizes a write operation in the addressing period that follows the reset period.
FIG. 7 shows waveforms for driving the PDP according to the prior art and explains the problems of the prior art. In FIG. 7, the (a) portion shows a waveform for driving the addressing electrodes Aj, the (b) portion shows a waveform for driving the sustaining electrodes Xi, and the (c) portion shows a waveform for driving the scanning electrodes Yi. The waveforms of the (a) to (c) portions are the same as those of FIG. 5. In FIG. 7, the (d) portion shows changes in the potential difference between the sustaining electrodes Xi and the scanning electrodes Yi, and the (e) portion shows changes in the potential difference between the addressing electrodes Aj and the scanning electrodes Yi. A dotted area in the (d) and the (e) portions indicates discharge caused by the potential difference.
The changes in the potential difference between the sustaining electrodes Xi and the scanning electrodes Yi of the (d) portion of FIG. 7 show that the polarity of the total write discharge pulse in the reset period is the same as that of the addressing pulse in the addressing period. If the self-erase discharge is unable to erase wall charges accumulated with the total write discharge, the remaining wall charges prevent the addressing discharge. This is the first problem shown in FIGS. 8(a) through 8(c).
The changes in the potential difference between the addressing electrodes Aj and the scanning electrodes Yi of the (e) portion of FIG. 7 show that the polarity of the total write discharge pulse in the reset period is the same as that of the addressing pulse in the addressing period. Originally, the 3-electrode surface-discharge PDP causes sustain discharge between the sustaining electrodes Xi and the scanning electrodes Yi formed on one of the substrates, and therefore, it is not easy for the prior art to erase wall charges accumulated on the addressing electrodes Aj. As a result, part of the wall charges accumulated on the addressing electrodes Aj with the addressing discharge remains even after the completion of the sustain discharge period. Since the polarity of the total write discharge pulse in the next reset period is the same as that of the addressing pulse in the addressing period, part of the remaining wall charges is not erased in the reset period, to interfere with the next addressing discharge. This is the second problem shown in FIGS. 9(a) through 9(e). The details of the first and second problems will be explained.
FIGS. 8(a) through 8(c) are models showing the total write discharge process, total self-erase discharge process, and addressing process, respectively, of the prior art and explaining the first problem of the prior art. In the total write discharge process of FIG. 8(a), the total write discharge pulse of Vs+Vw (about 300 V) is applied to the sustaining electrodes Xi. At this time, a voltage of, for example, 0 V is applied to the scanning electrodes Yi, and the pulse of raw (100 V) is applied to the addressing electrodes Aj. As a result, discharge occurs between the sustaining electrodes Xi and the scanning electrodes Yi, as well as between the sustaining electrodes Xi and the addressing electrodes Aj, to accumulate positive and negative wall charges on the electrodes depending on the applied voltages.
In the total self-erase discharge process of FIG. 8(b), 0 V is applied to all of the electrodes after the total write discharge pulse disappears. Then, self-erase discharge starts due to the potential difference between the positive and negative wall charges accumulated during the total write discharge process. The wall charges are neutralized to disappear. However, the wall charges around a gap or a counter slit between the electrodes that cause no discharge between them are not neutralized and partly remain. The counter slit is present between, for example, the first sustaining electrode X1 and the second scanning electrode Y2.
FIG. 8(c) shows the first problem occurring when the addressing process is carried out with the wall charges remaining. When addressing discharge is carried out, positive wall charges around the scanning electrodes Yi drop a voltage between the addressing electrodes Aj and the scanning electrodes Yi, to prevent the addressing discharge.
FIGS. 9(a) through 9(e) are models showing the addressing process, sustain discharge process, total write discharge process, total self-discharge process, and next addressing process of the prior art and explaining the second problem of the prior art. In the addressing process of FIG. 9(a), the voltage of Vx (50 V) is applied to the sustaining electrodes Xi, and the scanning pulse of -Vy (-150 V) is applied successively to the scanning electrodes Yi. At the same time, the addressing pulse of Va (50 V) is applied to selected ones of the addressing electrodes Aj according to display data, to carry out addressing discharge. This accumulates wall charges on the sustaining and scanning electrodes of each discharge cell to which data is to be written. The wall charges effectively act when sustain discharge is carried out between the sustaining and scanning electrodes of the cell later. During the addressing process, the addressing electrodes Aj used to select the discharge cells inevitably accumulate negative wall charges. The PDP of FIG. 2 forms the barriers 19 for spatially separating the discharge cells only along the addressing electrodes Aj, and therefore, the wall charges produced with the addressing discharge spread along the addressing electrodes Aj.
The sustain discharge process of FIG. 9(b) applies sustain discharge pulses additively to the wall charges that have been accumulated during the addressing process of FIG. 9(a) on the sustaining electrodes Xi and scanning electrodes Yi. Accordingly, sustain discharge occurs only between the sustaining electrodes Xi and the scanning electrodes Yi formed on one of the substrates, and therefore, the wall charges accumulated on the addressing electrodes Aj are hardly neutralized. In particular, the wall charges accumulated around the counter slits adjacent to the addressing electrodes Aj are away from discharge spaces between the sustaining electrodes Xi and the scanning electrodes Yi, and therefore, tend to remain even after the completion of the sustain discharge process.
Even after the total write discharge process of FIG. 9(c) and total self-erase discharge process of FIG. 9(d) in the next subframe, the wall charges around the counter slits adjacent to the addressing electrodes Aj remain. This is because the polarity of the potential difference between the addressing electrodes Aj and the scanning electrodes Yi is unchanged between the total write discharge process and the addressing process.
Generally, wall charges accumulated by discharge produced with a voltage having a given polarity are completely neutralized only by discharge produced with the same magnitude of voltage having an opposite polarity. When the total write discharge process of FIG. 9(c) applies a voltage having the same polarity as that of the addressing process of FIG. 9(a), the negative wall charges remaining around the addressing electrodes Aj drop the voltage applied in the total write discharge process between the addressing electrodes Aj and the scanning electrodes Yi. Since the voltage applied between the addressing electrodes Aj and the scanning electrodes Yi is low, for example, about 100 V in the total write discharge process, there will be no discharge between the addressing electrodes Aj and the scanning electrodes Yi. In this case, discharge mainly occurs between the addressing electrodes Aj and the sustaining electrodes Xi between which a high voltage is applied as shown in FIG. 9(c). The wall charges remaining around the counter slits along the addressing electrodes Aj are too far from discharge spaces between the addressing electrodes Aj and the sustaining electrodes Xi. As a result, the wall charges around the counter slits along the addressing electrodes Aj are not completely neutralized even through the total write discharge process of FIG. 9(c) and the total self-erase discharge process of FIG. 9(d).
The next addressing process of FIG. 9(e) applies the addressing pulse of Va (50 V) to selected ones of the addressing electrodes Aj. At this time, the negative wall charges remaining along the addressing electrodes Aj drop the voltage applied between the addressing electrodes Aj and the scanning electrodes Yi in the addressing process of FIG. 9(e). This results in no addressing discharge beginning in some of the discharge cells.
It has been known that such remaining wall charges cause a drop of an originally applied voltage by about 10 V, reducing the expected discharge. Namely, the remaining wall charges result in an applied voltage to not reach a required discharge start voltage, thereby producing no discharge. In this way, the prior art is unable to stably carry out addressing discharge. Due to this, the prior art causes write errors to incorrectly display data. To cope with the remaining wall charges, there has been proposed an idea to apply a large voltage to the electrodes. This, however, increases power consumption.